1. Field of the Invention
The present invention is related to high thermal emissive semiconductor device packages, and more particularly it is related to high thermal emissive structures which can be applied to high speed or high clock frequency devices such as application specific integrated circuits(ASICs), or fast memory devices so that they efficiently emit heat generated by electrical components.
2. Prior Art
Thermal emission is one of the very important properties required for semiconductor devices. Particularly, for high speed and high power semiconductor devices, thermal emission becomes more important.
The thermal emissive structures which are on-going developments or have been developed may be classified into two classes : (1) plastic pad array packages in which a power transistor or module is provided with a heat sink, and (2) metal housed ceramic substrates.
Most of the high speed and high power microprocessors, ASICs or fast memory devices have multi-pin input/output terminals, and the semiconductor devices employed for manufacturing these devices also should have a corresponding multi-pin configuration. For this purpose, plastic or ceramic pin grid array carrier packages, land grid array carrier packages, ball grid array carrier packages or quad flat carrier packages are employed.
However, applications of these carrier packages made of conventional materials to high power apparatus are restricted due to their poor thermal emissive properties.
Referring to FIG. 1, which shows one example of conventional thermal emissive semiconductor packages, in the form of a pin grid array carrier package, the package (10) consists of a ceramic substrate (11) having a plurality of signal input and output terminals (12), a semiconductor chip (14) having solder bumps (13) and being mounted on the ceramic substrate (11), a thermal compound (15) mounted onto the semiconductor chip (14), a metal cap (16) which encases the whole components, and a heat sink (17) mounted on the metal cap ((16).
In the package (10), heat generated during the operation of chip (14) is dissipated in directions indicated by arrows, and the heat moved upward is efficiently emitted by aid of the thermal compound (15).
Such structure is commonly applied to multi-chip module packages. However, this structure of packages has a problem that the formation of solder bumps (13) on the lower surface of the chip (14) for the purpose of mounting the chip (14) onto the ceramic substrate (11) is difficult to do.
Referring to FIG. 2, which shows another example of conventional cavity-down thermal emissive semiconductor packages, in the form of pin grid array carrier package, the package (20) consists of a ceramic substrate (21) which has a cavity at the central bottom and has a plurality of signal input and output terminals (22) at both ends, a semiconductor chip (24) which is back-bonded to the substrate (21) by a die-attach material (25) within the cavity, a lid (23) provided for protecting the chip (24) below the substrate (21), and a heat sink (27) which is mounted onto the substrate (21) by an interface material (28).
In the thermal emissive package (20) shown in FIG. 2, the heat is efficiently dissipated in the directions indicated by the arrows. However, this structure of package has a problem that a sufficient large number of pins can not be provided.
Referring to FIG. 3, which shows another example of conventional cavity-up thermal emissive semiconductor structures, in the form of a pin grid array carrier package, the package (30) consists of a ceramic substrate (31) which has a cavity at the central top and has a plurality of signal input and output terminals (32) at the lower surface, a semiconductor chip (34) which is back-bonded to the substrate (31) by a die-attach material (35) within the cavity, a lid (37) provided for protecting the chip (34) onto the substrate (31), and a heat sink (39) which is mounted onto the lid (37) by an interface material (38).
In the thermal emissive package (30) shown in FIG. 3, the heat is efficiently dissipated in the directions indicated by the arrows. However, this package has a drawback that heat dissipation is restricted because the heat generated from the upper surface of the chip (34) is dissipated through the lower surface of the chip (31) to the side surface of the chip (31).
Further, the above described packages (10), (20) and (30) are disadvantageous in that applications of these packages to other substrates than ceramic ones are restricted, due to complexicity of the manufacturing process.
In FIG. 4, another example of a thermal emissive ball grid array carrier package is illustrated. The package (40), which is disclosed in U.S. Pat. No. 5,216,278, comprises a carrier substrate (41) provided with a pair of filled vias (42), a solder mask (45) overlying the package mounting surface (46), a plurality of vias (43) in a plated wire layer (44) located in the both ends of the substrate (41), an electronic component (47) mounted on the die pad of the substrate (41), a wire (48) between the bonding pads on the electronic component (47) and wire layer (44), a thermal coupling layer (49) mounted on the upper surface of the electronic component (47), a heat spreader (51) mounted on the upper surface of the package (40), a molded package body (52), and solder balls (53), (54) formed on the lower surface of the solder mask (45).
In the ball grid array package shown in FIG. 4, the heat generated from the upper surface of the electronic component (47) is dissipated through the thermal coupling layer (49) and heat spreader (51), while the heat generated from the lower surface of the component (47) is dissipated to the vias (43). However, because the heat dissipation path is formed within a package body (52) molded with epoxy molding resin (EMC), of heat dissipation is not efficiently conducted. Further, it is difficult to form the thermal coupling layer (49) and heat spreader (51) on the upper surface of the electronic component (47) and to form solder balls on the lower surface of the component (47).
To avoid these prior art problems, there was proposed a package employing an immersion cooling chip as shown in FIGS. 5(A) and 5(B).
Referring to FIG. 5(A), there is shown a high thermal emissive package employing an immersion cooling chip, which comprises a multilayered ceramic substrate (61) having a cavity, a plurality of signal input and output terminals (62) formed on the lower surface of the substrate (61), a semiconductor chip (64) mounted within the cavity of the substrate (61), a dielectric liquid (65) filling the cavity, and a metal cap (66) covered the dielectric liquid.
Referring to FIG. 5(B), there is shown another high thermal emissive package employing an immersion cooling chip, which comprises a multilayered ceramic substrate (61) having a cavity, a plurality of signal input and output terminals (62) formed on the lower surface of the substrate (61), a semiconductor chip (64) mounted within the cavity of the substrate (61), a dielectric liquid (65) filling the cavity, an encapsulating metal cap (66), and a heat sink (67) mounted onto the metal cap (66).
For these packages, the heat generated during the operation of electronic components is dissipated via vaporization and condensation of the dielectric liquid. However, there is a severe restriction in heat dissipation, because the chip is not directly contacted to the metal cap on which the heat sink is optionally mounted.
Therefore, there are needs to be provided various efficient thermal transfer structures which can be applied to conventional carrier, pad array or cavity up type semiconductor device packages.